1. Technical Field
The present invention relates to a test apparatus, a probe card and a test method. More particularly, the present invention relates to a test apparatus and a test method for testing a device under test such as a semiconductor circuit, and to a probe card for use in the test apparatus.
2. Description of the Related Art
A known conventional test apparatus for testing a device under test such as a semiconductor circuit includes a plurality of driver/comparator pins that transmit/receive signals to/from the device under test. When the test apparatus supplies test signals to the device under test, each of the plurality of driver/comparator pins can generate a binary test signal and supply the generated binary test signal to the device under test. Here, the binary test signal may be, for example, a signal having a logic pattern formed by binary logic values such as H and L logic values.
When testing the device under test, the test apparatus may be required to supply a multiple-valued (three-valued or higher) test signal to the device under test. In response to this requirement, a driver/comparator pin which allows for multiple-valued test signal generation may be newly added to the test apparatus. This solution, however, increases the cost. Therefore, an alternative solution is suggested which uses the driver/comparator pins which have been already mounted to generate binary test signals for generating multiple-valued test signals.
FIG. 8 illustrates an example of a test apparatus 400 generating a multiple-valued test signal. The test apparatus 400 includes therein a pin electronics section 410 and a probe card 420. The pin electronics section 410 includes therein a plurality of drivers 412 and a plurality of comparators 414. Each driver 412 outputs a binary test signal.
The probe card 420 includes therein a plurality of transmission paths 422 and a needle 424. The transmission paths 422 are provided in a one-to-one correspondence with the drivers 412. Each transmission path 422 transmits therethrough a test signal output from a corresponding one of the drivers 412. The respective top ends of the transmission paths 422 are short-circuited in the probe card 420.
The needle 424 is fixed, by using a solder or the like, at one end thereof to the short-circuited transmission paths 422. The needle 424 is, at the other end thereof, in contact with a terminal of a device under test, so as to supply the test signals received via the transmission paths 422 to the device under test. With such a configuration, by causing the drivers 412 to output the test signals in synchronization with each other, the test apparatus 400 can combine together the test signals in the probe card 420, thereby supplying a multiple-valued test signal to the device under test.
For example, a case is assumed where each driver 412 generates a binary test signal indicating either the H logic (1V) or L logic (0V) and the test apparatus 400 short-circuits the outputs from two drivers 412 to generate a multiple-valued test signal. In this case, the combination signal can take one of three logic values (signal levels) including a logic value (0V) generated when the two drivers 412 both output the L logic, a logic value (0.5V) generated when one of the drivers 412 outputs the H logic and the other driver 412 outputs the L logic, and a logic value (1V) generated when the two drivers 412 both output the H logic.
By using the above-described configuration, it becomes possible to generate a multiple-valued test signal by using driver/comparator pins which are mounted on a conventional test apparatus for generating binary signals. When each transmission path 422 has a different delay amount, however, the test apparatus 400 can not generate an accurate multiple-valued test signal even though each driver 412 outputs the test signal at the same timing.
Therefore, the test apparatus 400 preferably measures in advance the delay amounts of the transmission paths 422, and adjusts the test signal output timings of the drivers 412 in accordance with the measured delay amounts of the transmission paths 422. The test apparatus 400 may measure the delay amounts of the transmission paths 422 by using a time domain reflectometry (TDR) method.
The TDR method measures the delay time of a transmission path by inputting a signal into the transmission path with its top end being kept open and measuring the delay time of the signal which is reflected at the open top end of the transmission path. Since the comparators 414 and the drivers 412 are connected to the same transmission paths 422 in the test apparatus 400, the test apparatus 400 can easily measure the delay times of the transmission paths 422 by referring to the timings at which the drivers 412 output the signals and the timings at which the comparators 414 detect the reflected waves.
Here, the top ends of the transmission paths 422 are short-circuited and fixed to the needle 424 by using a solder or the like in the test apparatus 400 which generates a multiple-valued test signal, as illustrated in FIG. 8. For this reason, the test apparatus 400 can not use the TDR method to measure the delay times of the transmission paths 422. Specifically speaking, the TDR method can not be used to measure the delay times of the transmission paths 422 since the reflected waves are not generated at the top ends of the transmission paths 422.
Note that the test apparatus 400 can measure the total of the delay times of the first and second transmission paths 422-1 and 422-2 by referring to the timing at which the first driver 412-1 outputs a signal and the timing at which the second comparator 414-2 detects the signal. However, the test apparatus 400 can not measure the delay time of each of the first and second transmission paths 422-1 and 422-2. Therefore, the test apparatus 400 has difficulties in adjusting the timing at which each driver 412 outputs a signal. As a result, it has been difficult for the test apparatus 400 to generate an accurate multiple-valued test signal.